PA-PRO-2019-012

Channel configuration registers of a full size prototype for the custom readout circuit of silicon
double-sided microstrips of PANDA Micro Vertex Detector were tested for upset effects. The
ASIC is developed with a commercial 110 nm CMOS technology and implements both the Triple
Modular Redundancy and the Hamming Encoding techniques. Results from tests with ion and
proton beams show the robustness level of these two techniques against the upset effects and allow
the evaluation of that commercial 110 nm technology in the PANDA experiment.