TA-CON-2022-030

Publication title: 

A 64 channels ASIC for the readout of the silicon strip detectors of the PANDA Micro-Vertex Detector

Publication author: 

Giovanni Mazza

File upload: 

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Publication type: 

Talk contribution: 

Publication classification: 

Publication date: 

Tuesday, 20 September, 2022

Publication abstract: 

The ToASt ASIC is a 64 channel integrated circuit designed for the readout of the Silicon Strips that will equip the Micro-Vertex Detector of the PANDA experiment. The ToASt ASIC is synchronous to a 160 MHz clock, which defines also the time resolution. A common time stamp is distributed to all channels to provide a common time reference for time of arrival and time over threshold measurements. Two 160 Mb/s serial lines provide the interface to the data concentrator. ToASt is implemented in a commercial 110 nm CMOS technology with triplicated logic to protect against single event upsets.