The future international accelerator facility FAIR (Facility for Antiproton and Ion Research) will host multiple experiments. A focus will be on experiments with antiprotons. The PANDA (antiProton ANnihilation at DArmstadt) experiment will study the strong interaction in annihilation reactions between an antiproton beam and a stationary gas jet target. The PANDA detector consists of different sub-detectors for tracking, particle identification and calorimetry. The Micro-Vertex Detector (MVD) as the innermost part of the tracking system will facilitate precise tracking and detection of secondary vertices. The MVD will comprise hybrid silicon pixel sensors and double-sided silicon strip sensors. The strip part will contain approximately 200,000 channels that need to be read out using a highly integrated front-end chip. Therefore, a custom-made ASIC is being developed. The self-triggering PASTA chip (PAnda STrip Asic) will employ the Time-over-Threshold (ToT) technique to digitize the hit amplitude and utilize time-to-digital converters (TDC) with analog interpolators to provide a high-precision time stamp of the hit. A custom-made Module Data Concentrator ASIC (MDC) will multiplex the data of all front-ends of one double-sided strip sensor towards the CERN-developed GBT chip set (GigaBit Transceiver). The MicroTCA-based MVD Multiplexer Board (MMB) at the off-detector site will receive and concentrate the data from the GBT links and transfer it to FPGA-based compute nodes for global event building that combines all sub-detectors.

ToPiX v4 is the prototype for the readout of the silicon pixel sensors for the Micro Vertex Detector of the PANDA experiment. ToPiX provides position, time and energy measurement of the incoming particles and is designed for the triggerless environment foreseen in PANDA. The prototype includes 640 pixels with a size of 100 um x 100 um, a 160 MHz time stamp distribution circuit to measure both particle arrival time and released energy (via ToT technique) and the full control logic. The ASIC is designed in a 0.13 um CMOS technology with SEU protection techniques for the digital parts.